Book/Dissertation / PhD Thesis

FZJ-2019-02708

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Configurable frequency synthesizer for large scale physics experiments

Parkalian, N. (Corresponding author)FZJ*

2019
Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag Jülich
ISBN: 978-3-95806-393-8

Please use a persistent id in citations: http://hdl.handle.net/2128/22152  urn:nbn:de:0001-2019050207

Abstract: This thesis describes the design and implementation of frequency synthesizers for the ”Jiangmen Underground Neutrino Observatory (JUNO)” project as a physical experiment. The fully integrated analog phase-locked loop (PLL) based frequency synthesizer is intended to generate the sampling clocks for the analog-to-digital converters (ADC) and digital signal processing (DSP) part. They are employed in the read-out electronics to be used in a neutrino experiment. The proposed design was fabricated in 65 nm CMOS technology. The design provides the best compromise between noise, power consumption and area for a highly reliable and configurable operation based on the application requirements. The design procedure for the PLL architecture and different sub-blocks are presented. A 4 GHz LC-based voltage controlled oscillator (VCO) is suggested for the low noise operation while providing an optimum tuning range to increase the linearity and frequency coverage in case of process-voltage-temperature (PVT) changes. Furthermore, a novel technique for the amplitude regulation is suggested to detect amplitude errors at the outputs of the VCO and provide an optimized range for the amplitude for a low noise and reliable design. In addition, a new approach for the charge pump is introduced that suppresses the associated current mismatch problem of conventional structures. This minimizes the static phase error at the input of the PLL that causes spurs at the output. The measurement results of the analog PLL show very good performance of the structure based on the required specifications and confirm the simulations. The total power consumption for the PLL core equals to 18.5 mW at 1.8 V supply for the VCO and 1 V supply for the other blocks. [...]

Note: Universität Duisburg, Diss., 2019

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Contributing Institute(s):

1. Zentralinstitut für Elektronik (ZEA-2)

Research Program(s):

1. 899 - ohne Topic (POF3-899) (POF3-899)

Appears in the scientific report 2019

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